NES Emulator documentation

This documentation details my implementation of an NES. However, as of now, only the CPU is in a usable condition.

The goal of this project is to develop a VHDL code which can be synthetised on an arbitrary FPGA chip to emulate the behavior of an NES.

• 1. CPU
  • 1.1. 6502 CPU
    • 1.1.1. ALU
    • 1.1.2. ID
    • 1.1.3. Memory
    • 1.1.4. Registers
    • 1.1.5. Instructions
    • 1.1.6. Addressing modes
    • 1.1.7. Pinout
    • 1.1.8. Microcode
    • 1.1.9. State machine
  • 1.2. APU
• 2. PPU

[MOS Technology, Inc.75]

MCS6501 - MCS6505 MICROPROCESSORS. MOS Technology, Inc., 1975.

[MOS Technology, Inc.76a]

MCS6500 MICROCOMPUTER FAMILY HARDWARE MANUAL. MOS Technology, Inc., 1976.

[MOS Technology, Inc.76b]

MCS6500 MICROCOMPUTER FAMILY SOFTWARE MANUAL. MOS Technology, Inc., 1976.

[Car84]

Joseph J. Carr. 6502 User's Manual. Reston Pub. Co., 1984.

[Inc75]

Mos Technology Inc. Integrated circuit microprocessor with parallel binary adder having on-the-fly correction to provide decimal results. 1975. URL: https://patents.google.com/patent/US3991307.

[Kes99]

David Kessner. Free-6502. 1999. URL: https://www.sprow.co.uk/dump/index.htm#Free6502.

[Mor12]

Nick Morgan. Easy 6502. 2012. URL: https://skilldrick.github.io/easy6502/.

[Qui11]

Quietust. Chip images. 2011. URL: https://www.qmtpro.com/~nes/chipimages/index.php.

[Tay04]

Brad Taylor. 2a03 technical reference. 2004. URL: https://www.nesdev.org/2A03%20technical%20reference.txt.